We were anal about chip size at the circuit design level. Smaller chips equalled more die per wafer and lower die cost. I suppose this being attached to a drive and its outline determines max overall board area - and if there is plenty of real estate available I can see why designing in large test points is no big deal. We tried every trick to reduce die size, even locating circuitry under the bond pads. Extra available real estate was a foreign concept. Let me be first to congratulate you on your fortcoming redpill! Do you think you will get there by end of day?